[Eecs_bscs] EECS Research Seminar Talk with ASCENT Visiting Professor Interview Candidate Talha Furkan Canan-Designing novel gate work function engineered FinFETs for CMOS scaling, hardware security and neuromorphic computing

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Title: Designing novel gate work function engineered FinFETs for CMOS scaling, hardware security and neuromorphic computing

Abstract: Scaling CMOS logic circuits to build low power and compact devices has utmost importance in modern CMOS technology. Schottky Barrier FinFET transistors can offer a solution for sub 10nm transistor design as it affects the process minimally. Gate workfunction engineered Schottky Barrier FinFETs can be used to minimize the number of transistors used in a CMOS digital circuit, making it power and area efficient while staying competitive for power delay product. Characterization of Schottky Barrier FinFETs for very large system integration involves different steps from device level to system level abstraction. Gate work function engineered Schottky Barrier FinFETs can also be utilized to build multi input logic circuits and fine grain reconfigurable logic circuits which are especially important for hardware security applications. Extending the idea of gate work function engineering to tunneling transistors can lead to ultra low power and ultra fast green transistors reaching beyond 60mV/decade thermodynamic limit of thermionic emission. For the future research work, gate work function engineered SiGe based tunneling FETs may be useful for in-memory computing in the area of neuromorphic computing.

Bio: Talha Furkan Canan received the B.S. degree from Department of Electrical and Electronics Engineering, Bilkent University, Ankara, Turkey, in 2015. Following his work as research engineer in CAD modelling of GaN HEMT devices at the Nanotechnology Research Center in Bilkent University, he joined Ohio University in 2016 to commence his Ph.D. work on nano-scale CMOS integrated systems, logic devices and interconnects for kilocore computing architectures. He prepared his dissertation on "Design of Ultra-Compact and Low-Power sub-10 Nanometer Logic Circuits with Schottky Barrier Contacts and Gate Work-Function Engineering". After receiving his Ph.D. degree, he joined Sony Electronics Image Sensor Design Center and worked on different technical projects related with unit pixel scaling, single photon avalanche photodiode design, conversion gain improvement and optical characterization of image sensors. His research interests include design of ultra low power and compact logic circuits, tunneling transistors, III-V and III-N semiconductor devices, CMOS image sensors, avalanche photodiodes, hardware security, thin-film transistors and hot electron and ionization diodes. Dr. Canan is an expert on semiconductor electronics and device simulations with more than ten years of professional experience. He was a recipient of G.E. Smith and G.V. Smith Memorial Engineering Award for Electrical Engineering and Computer Science Department at Ohio University at 2021 and Nanoscale Quantum Phenomenon Institute Award at 2019. Currently, he has one patent and twelve publications including five journal papers.
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