[Eecs_mscs] EE 6900: Interconnection Networks for HPC Systems and Accelerators

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EE 6900: Interconnection Networks for HPC Systems and Accelerators

EE 6900 is intended to provide graduate students with an in-depth study of interconnection networks for high-performance computing (HPC) systems, multi-cores and hardware accelerators. Interconnection networks offer an attractive and economical solution to this communication crisis and are fast becoming pervasive at all levels of digital system, whether it be on-chip, inter-chip, inter-board and inter-rack. As machine learning based accelerators begin to dominate the market, this course will also analyze the impact of data movement for deep learning applications. Emerging technologies such as photonics and wireless will also be discussed.

Topics covered include:

[1] Introduction to Interconnection Networks

[2] Topology

[3] Switching Techniques

[4] Taxonomy of Routing Algorithms

[5] Flow Control

[6] Router Micro-architecture

[7] Hardware Accelerators for Deep Learning
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Avinash Karanth

Chair, School of Electrical Engineering and Computer Science

Joseph K. Jachinowski Professor in EECS

Associate Editor - IEEE Transactions on Computers

Associate Editor - IEEE Transactions on Cloud Computing

Ohio University, Athens, OH 45701.

Phone: 740-597-1481

Fax: 740-593-0007

Webpage: https://oucsace.cs.ohio.edu/~avinashk 
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